This invention relates to a semiconductor memory device capable of carrying out a random access operation and a serial access operation. Such a semiconductor memory device is particularly useful in a data processing system comprising a microprocessor.
As an example of a semiconductor memory device, a dynamic random access memory device is described in an article which is published by Syoji Ishimoto et al under the title of "SPECIAL APPLICATION MEMORIES" in "1985 IEEE International Solid-State Circuits Conference", pages 38 and 39, Feb. 13, 1985. Such a dynamic random access memory device is used as a memory device for a microprocessor in a data processing system. Generally, the dynamic random access memory device comprises a plurality of memory cells which are arranged on a cell area defined by a plurality of column signal lines and a plurality of row signal lines, a column decoder, a row decoder, a random access section, and a serial access section. The plurality of column signal lines are connected to a plurality of sense amplifiers, respectively. The random access section is for carrying out a random access operation for accessing at least one of the plurality of memory cells at random in cooperation with the column decoder and the row decoder. The serial access section is for carrying out a serial access operation for serially and collectively accessing a part of the plurality of memory cells, in cooperation with the row decoder, those are arranged along one of the plurality of row signal lines.
With regard to a readout operation by the random access section, at least one item of data is read on at least one of the plurality of column signal lines, and amplified into random readout data by the sense amplifier which is connected to the above-mentioned one of the plurality of column signal lines. The random access section transfers the random readout data as random access data to an outer unit, such as a central processing unit of the microprocessor. With regard to the readout operation by the serial access section, serial data are read on the plurality of column signal lines at a time and amplified into serial readout data by the plurality of sense amplifiers, at a time, which are connected to the plurality of column signal lines, respectively. The serial access section transfers the serial readout data as serial access data to the outer unit.
Although the data processing speed of the microprocessor is on an upward trend, it is restricted by an access speed of the dynamic random access memory device. The access speed of the dynamic random access memory device is influenced by the data transfer time of the random or serial access data. In other words, if the data transfer time can be reduced, it is possible to increase the data processing speed. In order to increase the data processing speed, various improvements have been made on dynamic random access memory devices. For example, a data register is combined with the serial access section for temporarily storing the serial readout data in order to increase the access speed. Such a dynamic random access memory device will be called a first type for convenience.
In such a first type, although the access speed can be increased by the use of the data register, the data register causes the following problem in the serial access operation. Namely, a high peak current momentarily flows through the dynamic random access memory device. This is because the serial access section collectively activates the part of the plurality of memory cells arranged along one of the plurality of row signal lines. This means that all of the plurality of sense amplifiers connected to the plurality of column signal lines are put into an active state at one time, and that the serial readout data are collectively stored into the data register.
In order to solve the above-mentioned problem, a semiconductor memory device of another type is described in Japanese Unexamined Patent Publication Tokkai Hei 4-195886, namely, 195886/1992. Such a semiconductor memory device will be called a second type. In the second type, the data register is divided into first and second partial data registers. The first partial data register is for storing a first half of the serial readout data held in one part of the plurality of memory cells, while the second partial data register is for storing a second half of the serial readout data held in the other part of the plurality of memory cells. The first and the second halves of the serial readout data are time divisionally stored into the first and the second partial data registers. In other words, the first half of the serial readout data are stored into the first partial data register at a first time. At a second time, delayed from the first time, the second half of the serial readout data are stored into the second partial data register. As a result, the peak current caused by the data register is reduced by half relative to the first type.
However, the problem of the peak current caused by the plurality of sense amplifiers is not yet solved in the second type. This is because all of the plurality of sense amplifiers connected to the plurality of column signal lines are put into the active state at one time.